The present invention generally relates to semiconductor integrated circuits, and more particularly, to methods for mitigating topographic defects in graphoepitaxy directed self-assembly processes.
Block co-polymer (BCP) lithography is becoming an established directed self-assembly technique for patterning beyond optical lithography limitations. It is based on combining the intrinsic property of block co-polymers to phase separate at the molecular scale with the capabilities of conventional top-down lithographic methods for patterning surfaces. Guiding the self-assembly of block co-polymers by surface chemical modification is one of the most used processes to drive the self-assembly in a convenient way. It typically consists of using lithography and oxygen plasma to create different wettability regions on a polymer brush material grafted on the surface.
In the graphoepitaxy directed self-assembly process, the self-organization of block copolymers is guided by topographical guiding patterns such that the block-copolymer self organizes in useful domains, which is dominated by the concept of confinement. Neutral walls or pillars that define the guiding pattern prevent certain chain configurations, which then lead to the polymer to adjust its periodic structures along a pre-determined axis. As a result, graphoepitaxy directed self-assembly provides sub-lithographic, self-assembled features having a smaller characteristic dimension than that of the pre-pattern itself.